In recent years, the explosion in growth of network traffic has pushed serial data links to higher and higher rates. As a result, SERDES (serializer-deserializer) circuitry is required to be clocked at greater frequencies resulting in significant power dissipation in clock distribution and routing. Typically, in these systems a low-jitter, high-frequency clock is generated from a central phase-locked loop (PLL) and then distributed to critical circuitry such as a link's high-speed transmitter and receiver, as shown in FIG. 1.
The sub-blocks shown in FIG. 1 can be located a significant distance away from this PLL and thus, these clocks dissipate significant power as they are rebuffered across the integrated circuit (IC). Moreover, in multi-lane architectures high-speed clocks from a central PLL may be routed up to several millimeters to reach parallel SERDES TX-RX slices. Distributing CMOS clocks at rates of >20 GHz across far distances can easily dissipate 10's of mW and be a significant source of power consumption. With increasing data rates and associated clock frequencies, this problem will continue to get worse in the future.
It is, therefore, desirable to provide a clock distribution network for distributing a clock signal that addresses at least one drawback of existing approaches.